Semiconductor device including detector circuit capable of performing high-speed operation

ABSTRACT

A detector circuit and a negative voltage generating circuit capable of performing a high-speed operation are provided. A negative voltage generating circuit includes a charge pump circuit, a first voltage divider circuit that makes a voltage division between an output of the charge pump circuit and a power supply to output a detect potential, a reference voltage generating circuit that generates a reference potential, and a comparator circuit that compares the detect potential and the reference potential. The charge pump circuit is driven by an output signal of the comparator circuit and generates the negative voltage. In the first voltage divider circuit, NMOS transistors make the voltage division between the negative voltage and the power supply to obtain the detect potential.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and especiallyto a negative voltage generating circuit and a detector circuit providedtherein.

2. Description of the Background Art

Usually, a semiconductor device including a DRAM (Dynamic Random AccessMemory) is provided with negative voltage generating circuitry forgenerating a voltage that is negative and lower than the ground (GND)potential (hereinafter referred to as a negative voltage). The negativevoltage is used as a substrate bias potential and controls thetransistor substrate effect. For example, in a DRAM that uses a PMOStransistor as a memory cell transfer gate, the negative voltage is usedas a voltage for driving the transistor (activation voltage). It isnecessary to set the transistor driving voltage sufficiently low, inorder to write a ground-level signal to the memory cell during write andto extract a signal voltage with a sufficient amplitude from the memorycell during read.

In general, when a negative voltage generated by a negative voltagegenerating circuit is used as a substrate bias potential, potentialvariations are suppressed by large capacitance of the substrate, and thenegative voltage generating circuit is not required to providehigh-speed response. However, when the semiconductor device using thenegative voltage as a transistor driving voltage is operated at highspeed, the current consumption related to the negative voltage is largeand therefore high-speed response of the negative voltage generatingcircuit is needed. Steadily supplying the negative voltage even when thecurrent consumption related to the negative voltage is large requiresquickly detecting potential variations of the negative voltage andfeeding power (supplying charge).

Conventional negative voltage generating circuits are disclosed inJapanese Patent Application Laid-Open Nos. 10-239357 (1998) and11-312392 (1999), for example. The negative voltage generating circuitdescribed in Japanese Patent Application Laid-Open No. 10-239357, forexample, includes a charge pump circuit for generating a negativevoltage and a detector circuit for detecting the potential of thenegative voltage (which is referred to also as “a negative voltagesensing circuit” or “a level detecting circuit”). When detecting thenegative voltage becoming higher than a desired value because of currentconsumption, the detector circuit activates the charge pump circuit tosupply charge to the negative voltage output so that the negativevoltage keeps the desired value.

In conventional negative voltage generating circuits, the detectorcircuits do not have high-speed response. Accordingly, when thesemiconductor device using the negative voltage as a transistor drivingvoltage is operated at high speed, the detector circuit may fail tosufficiently follow instantaneous variations of the negative voltage,which leads to unstable supply of the negative voltage.

Also, breakdown voltages of semiconductor devices are becoming lowerbecause of recent downsizing of LSIs, i.e., miniaturization oftransistors, which unavoidably leads to lower operating voltages(power-supply voltages). Moreover, battery-driven portable devices, forexample, demand reduction of power consumption through reduction ofoperating voltage and reduction of consumption current. However, loweroperating voltage further deteriorates the detector circuit response andreduces the stability of the negative voltage generating circuit. Thishinders reduction of power consumption of the semiconductor devices.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a semiconductor deviceincluding a detector circuit that is capable of performing stablehigh-speed operation and a negative voltage generating circuit havingthe detector circuit.

In an aspect of the invention, a semiconductor device includes adetector circuit that detects a level of a negative voltage. Thedetector circuit includes: a first voltage divider circuit that outputsa detect potential generated by a voltage division made by a pluralityof MOS transistors connected in series between a potential of thenegative voltage and a positive power-supply potential; and a comparatorcircuit that compares the detect potential and a predetermined referencepotential.

The first voltage divider circuit included in the detector circuit iscomposed of a plurality of MOS transistors. Accordingly, the detectpotential quickly varies following a variation of the negative voltagebecause of the effect of capacitive coupling by the gate capacitance andparasitic capacitance of the MOS transistors. This enables thecomparator circuit to detect the variation of the negative voltagequickly, thus offering high-speed response.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating the configuration of a negative voltagegenerating circuit according to a first preferred embodiment;

FIGS. 2A, 2B and 3 are diagrams used to describe a negative voltagegenerating circuit according to a third preferred embodiment;

FIG. 4 is a diagram illustrating the configuration of a comparatorcircuit of a negative voltage generating circuit according to a fourthpreferred embodiment;

FIG. 5 is a diagram illustrating the configuration of a comparatorcircuit of a negative voltage generating circuit according to a fifthpreferred embodiment;

FIG. 6 is a diagram illustrating the configuration of a negative voltagegenerating circuit according to a sixth preferred embodiment;

FIG. 7 is a diagram showing a modification of the comparator circuit ofthe negative voltage generating circuit according to the sixth preferredembodiment;

FIG. 8 is a diagram illustrating the configuration of a negative voltagegenerating circuit according to a seventh preferred embodiment;

FIG. 9 is a diagram illustrating the configuration of a negative voltagegenerating circuit according to an eighth preferred embodiment;

FIGS. 10 to 12 are diagrams showing examples of the configuration of afirst voltage divider circuit according to a ninth preferred embodiment;

FIG. 13 is a circuit diagram of conventional word line driver and DRAMcell;

FIG. 14 is a cross-sectional view of the conventional word line driverand DRAM cell;

FIG. 15 is a circuit diagram of a word line driver and a DRAM cellaccording to a tenth preferred embodiment;

FIG. 16 is a cross-sectional view of the word line driver and the DRAMcell according to the tenth preferred embodiment;

FIG. 17 is a circuit diagram of a first voltage divider circuitaccording to the tenth preferred embodiment; and

FIG. 18 is a cross-sectional view of the first voltage divider circuitaccording to the tenth preferred embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention will now bedescribed. In this specification, for the sake of simplicity ofdescription, when the potential of a negative voltage is low (i.e., whenthe absolute value of the negative voltage is large), it may beexpressed as “the negative voltage is deep”. On the other hand, when thepotential of the negative voltage is high (i.e., when the absolute valueof the negative voltage is small), it may be expressed as “the negativevoltage is shallow”.

First Preferred Embodiment

FIG. 1 is a diagram illustrating the configuration of a negative voltagegenerating circuit included in a semiconductor device according to afirst preferred embodiment of the present invention. As shown in FIG. 1,the negative voltage generating circuit includes a charge pump circuit1, a detector circuit 2, and a reference voltage generating circuit 3.

The charge pump circuit 1 is driven by an output signal of the detectorcircuit 2 (“detect signal S_(DET)” described later) and generates andoutputs a predetermined negative voltage V_(NEG).

The detector circuit 2 includes a first voltage divider circuit 21 and acomparator circuit 22. The first voltage divider circuit 21 includes twodiode-connected NMOS transistors N1 and N2, where the NMOS transistorsN1 and N2 make a voltage division between the output of the charge pumpcircuit 1 (the negative voltage V_(NEG)) and a power supply V_(DD) as apositive potential, and the first voltage divider circuit 21 outputs theobtained potential V_(DIV) (the potential at a node connecting the NMOStransistor N1 and the NMOS transistor N2, which is hereinafter referredto as “detect potential V_(DIV)”).

In this preferred embodiment, the channel width sizes of the NMOStransistors N1 and N2 are set equal to each other. That is, the voltagedivision ratio of the first voltage divider circuit 21 is ½ and thedetect potential V_(DIV) is given as V_(DIV)=(V_(DD)+V_(NEG))/2. Thedetect potential V_(DIV) is inputted to the comparator circuit 22.

The comparator circuit 22 compares the detect potential V_(DIV)outputted from the first voltage divider circuit 21 and a predeterminedreference potential V_(REF) outputted from the reference voltagegenerating circuit 3 to detect the level of the negative voltageV_(NEG). That is, when the negative voltage V_(NEG) is deeper than agiven value, the detect potential V_(DIV) is smaller than the referencepotential V_(REF) and the detect signal S_(DET) outputted from thecomparator circuit 22 is kept at an L (Low) level. When the negativevoltage V_(NEG) becomes shallower than a given value, the detect signalS_(DET) varies to an H (High) level.

As shown in FIG. 1, the comparator circuit 22 includes a comparator CPand inverters I1 to I3 provided in its output stage. The inverters I1 toI3 wave-shape an output voltage V_(C) from the comparator CP to convertit into the detect signal S_(DET) as a logical signal.

The comparator CP includes PMOS transistors P1 and P2 forming adifferential pair, NMOS transistors N3 and N4 forming a current mirrorcircuit as a load, and a PMOS transistor P3 functioning as aconstant-current source. That is, the comparator CP is a so-called“current mirror type differential amplifier”.

Also, a PMOS transistor P5 is provided to give a constant current to theinverter I1 (a PMOS transistor P4 and an NMOS transistor N5) thatreceives the output voltage V_(C) from the comparator CP. A constantvoltage V_(CON) is applied to the gates of both of the PMOS transistorP3 and the PMOS transistor P5.

In this circuit configuration, the response speeds of the comparator CPand the inverter I1 are determined by the magnitudes of the currentssupplied through the PMOS transistors P3 and P5. That is, by keeping thevoltage V_(CON) constant, the response speeds of the comparator CP andthe inverter I1 are kept constant without depending on the voltage ofthe power supply V_(DD).

The PMOS transistors P3 and P5 function also to restrict to given valuesthe through currents flowing from the power supply V_(DD) to the groundGND through the comparator CP and the inverter I1, thereby suppressingthe current consumption of the comparator CP and the inverter I1. Thecurrent values supplied from the PMOS transistors P3 and P5 can beadjusted by adjusting the magnitude of the voltage V_(CON) applied totheir gates or by adjusting the channel width sizes.

As mentioned earlier, the charge pump circuit 1 is driven by the detectsignal S_(DET). That is, the charge pump circuit 1 is activated when thedetect signal S_(DET) attains the H level, and then supplies charge tothe output node to deepen the negative voltage V_(NEG). When thenegative voltage V_(NEG) becomes deeper than a particular value, thedetect signal S_(DET) goes to the L level and then the charge pumpcircuit 1 is inactivated and stops the supply of charge. The charge pumpcircuit 1 thus operates according to the detect signal S_(DET) so as tokeep the negative voltage V_(NEG) at a value based on the level of thereference potential V_(REF).

The reference voltage generating circuit 3, for generating the referencepotential V_(REF), includes a second voltage divider circuit 31 and abuffer circuit 32. The second voltage divider circuit 31 includes tworesistors R1 and R2, where the resistors R1 and R2 make a voltagedivision between the ground GND and the power supply V_(DD) and thesecond voltage divider circuit 31 outputs the obtained predeterminedpotential V_(REFO) (the potential of a node connecting the resistor R1and the resistor R2).

In this preferred embodiment, the resistance values n [Ω] and m [Ω] ofthe resistors R1 and R2 in the second voltage divider circuit 31 are setequal to each other. That is, the voltage division ratio is 1/2 as inthe first voltage divider circuit 21, and V_(REFO)=V_(DD)/2. Thepotential V_(REFO) outputted from the second voltage divider circuit 31is inputted to the buffer circuit 32 (adjustment circuit). The buffercircuit 32 makes the magnitude of the potential V_(REFO) smaller by apredetermined adjustment value and outputs it as the reference potentialV_(REF).

As shown in FIG. 1, the buffer circuit 32 includes PMOS transistors P6to P11 and NMOS transistors N6 to N9. The transistors P10 and P11, bothreceiving a constant voltage V_(CON) at their gates, pass constantcurrent to the buffer circuit 32 and restrict the through currentflowing through the buffer circuit 32 to suppress current consumption.The current values supplied from the PMOS transistors P10 and P11 can beadjusted by adjusting the magnitude of the voltage V_(CON) applied totheir gates or by adjusting the channel width sizes.

When the channel width sizes of the PMOS transistors P6, P7, P8 and P9and the NMOS transistors N6, N7, N8 and N9 are defined as W_(P6),W_(P7), W_(P8), W_(P9), W_(N6), W_(N7), W_(N8) and W_(N9), and thegradient of the transistors' I_(ds)−V_(g) characteristic (I_(ds):drain-source current, V_(g): gate voltage) in the sub-threshold region,with the logarithm of I_(ds), is defined as S (the quantity of variationof the gate voltage required for a one-digit variation of the current(the so-called S factor)), then the reference potential V_(REF)outputted from the buffer circuit 32 is given as:

V _(REF) =V _(REFO) +S×log((W _(P7) ×W _(N6) ×W _(P9) ×W _(N8))/(W _(N7)×W _(P6) ×W _(N9) ×W _(P8))).

Where, when the channel width sizes of the PMOS transistors P6 to P9 andthe NMOS transistors N6 to N9 are set as:

(W_(P7)×W_(N6)×W_(P9)×W_(N8))<(W_(N7)×W_(P6)×W_(N9)×W_(P8)),

then the reference potential V_(REF) is lower than the output potentialV_(REFO) of the second voltage divider circuit 31. Then, when adefinition is given as:

ΔV=|S×log((W _(P7) ×W _(N6) ×W _(P9) ×W _(N8))/(W _(N7) ×W _(P6) ×W_(N9) ×W _(P8)))|,

the expression of the reference potential V_(REF) is given as:

V _(REF) =V _(REFO) −ΔV.

That is, ΔV corresponds to the “adjustment value” mentioned above.

The reference potential V_(REF) outputted from the buffer circuit 32 isinputted to the comparator circuit 22 (the comparator CP). The capacitorC1 is provided to stabilize the reference potential V_(REF).

The operation of the negative voltage generating circuit according tothe preferred embodiment will be described below. In this preferredembodiment, V_(DIV)=(V_(DD)+V_(NEG))/2 andV_(REF)=V_(REFO)−ΔV=V_(DD)/2−ΔV, so that the detector circuit 2 outputsthe detect signal S_(DET) at the H level when V_(NEG)/2>−ΔV, and outputsthe detect signal S_(DET) at the L level when V_(NEG)/2<−ΔV. That is,the detector circuit 2 operates to detect the negative voltage V_(NEG)so that V_(NEG)=−ΔV×2.

The detect signal S_(DET) outputted from the detector circuit 2 isinputted to the charge pump circuit 1, and the charge pump circuit 1 isdriven by the detect signal S_(DET). When the negative voltage V_(NEG)is shallower than −ΔV×2, the detect signal S_(DET) is at the H level andthe charge pump circuit 1 is activated to deepen the negative voltageV_(NEG). When the negative voltage V_(NEG) reaches −ΔV×2 and the detectsignal S_(DET) goes to the L level, the charge pump circuit 1 is theninactivated and stops the supply of charge to the negative voltageV_(NEG) output node. The negative voltage generating circuit thus keepsthe output of the negative voltage V_(NEG) so that V_(NEG)=−ΔV×2.

As is known from the description above, the value of the negativevoltage V_(NEG) outputted from the negative voltage generating circuitof the preferred embodiment can be adjusted by varying the value of ΔVby adjusting the channel width sizes of the PMOS transistors P6 to P9and the NMOS transistors N6 to N9 of the buffer circuit 32.

When the negative voltage V_(NEG) instantaneously varies because of,e.g., current consumption of the device that uses the negative voltageV_(NEG) as a driving voltage, the detect potentialV_(DIV)(=(V_(DD)+V_(NEG))/2) varies. According to the present invention,since the first voltage divider circuit 21 is composed of the NMOStransistors N1 and N2, the detect potential V_(DIV) quickly variesfollowing the variation of the negative voltage V_(NEG) because of theeffect of capacitive coupling by the gate capacitance and parasiticcapacitance of the NMOS transistors N1 and N2. This offers high-speedresponse superior to those of conventional detector circuits.

Also, as described earlier, the response speeds of the comparator CP andthe inverter I1 are determined by the magnitudes of the currentssupplied through the PMOS transistors P3 and P5, and are hardly affectedby the power-supply voltage V_(DD). For example, increasing the currentflowing to the comparator CP shortens the charging/discharging time ofthe input gate of the next-stage inverter I1, which enhances thehigh-speed response of the comparator CP. Also, the high-speed responseof the inverter I1 can be enhanced by increasing the current flowing tothe inverter I1. Thus, the negative voltage generating circuit of thepreferred embodiment is capable of performing high-speed operation evenwhen the power-supply voltage is low.

However, as mentioned earlier, the PMOS transistors P3 and P5 have afunction of suppressing the current consumption by restricting thecurrents flowing in the comparator CP and the inverter I1 to givenvalues, and therefore it is not preferred that the PMOS transistors P3and P5 supply excessively large current values. Accordingly, it isdesirable to properly set the current values in accordance with thepurpose of use of the negative voltage generating circuit. The currentvalues supplied from the PMOS transistors P3 and P5 can be controlled byadjusting the magnitude of the voltage V_(CON) applied to the gates ofthe PMOS transistors P3 and P5 or by adjusting the channel width sizesof the PMOS transistors P3 and P5.

As described so far, according to this preferred embodiment, the NMOStransistors N1 and N2 in the first voltage divider circuit 21 make avoltage division between the power supply V_(DD) and the negativevoltage V_(NEG) to obtain the detect potential V_(DIV), so that thedetect potential V_(DIV) quickly responds to variations of the negativevoltage V_(NEG). Also, the response speeds of the comparator CP and theinverter I1 are independent of the voltage of the power supply V_(DD)and are determined by the current values supplied from the PMOStransistors P3 and P5. Therefore, the detector circuit 2 and thenegative voltage generating circuit including the detector circuit 2 arecapable of performing high-speed operation even when the power-supplyvoltage is low. This contributes to achievement of higher-speedoperation of the semiconductor device and reduction of powerconsumption.

Second Preferred Embodiment

In the first preferred embodiment, the voltage division ratio of thefirst voltage divider circuit 21 and the voltage division ratio of thesecond voltage divider circuit 31 are set equal to each other. In thiscase, the value of the negative voltage V_(NEG) outputted from thenegative voltage generating circuit does not depend on the potential ofthe power supply V_(DD). In the first preferred embodiment, for example,the voltage division ratio of the first voltage divider circuit 21 andthe voltage division ratio of the second voltage divider circuit 31 areboth 1/2, and therefore V_(NEG)=−ΔV×2, which shows that the negativevoltage V_(NEG) does not depend on the potential of the power supplyV_(DD).

On the other hand, in a second preferred embodiment, the resistancevalue of the resistor R1 of the second voltage divider circuit 31 andthe resistance value of the resistor R2 are set at different values sothat the negative voltage V_(NEG) varies depending on the potential ofthe power supply V_(DD).

That is, in this preferred embodiment, the voltage division ratio of thesecond voltage divider circuit 31 is adjusted to be different from thevoltage division ratio (1/2) of the first voltage divider circuit 21.Herein, for the sake of simplicity, the voltage division ratio of thefirst voltage divider circuit 21 is left at 1/2, but the value of thevoltage division ratio of the first voltage divider circuit 21 may beadjusted. However, adjusting the voltage division ratio of the secondvoltage divider circuit 31 is easier because changing the voltagedivision ratio of the first voltage divider circuit 21 requires changingthe channel width sizes of the NMOS transistors N1 and N2.

When the resistance values of the resistors R1 and R2 of the secondvoltage divider circuit 31 are represented respectively as n [Ω] and m[Ω] (n≠m), then the output potential V_(REFO) of the second voltagedivider circuit 31 is given as:

V _(REFO) =V _(DD) ×m/(m+n)=V _(DD)/2−V _(DD)×(n−m)/(2n+2m).

From the relation V_(REF)=V_(REFO)−ΔV, the detect potential of thedetector circuit 2, i.e., the negative voltage V_(NEG) outputted fromthe negative voltage generating circuit, is given as:

V _(NEG)=(−V _(DD)×(n−m)/(2n+2m)−ΔV)×2.

As is known from the expression, the negative voltage V_(NEG) hasdependence on the power-supply potential V_(DD) when n×m.

Now, when m<n, the negative voltage V_(NEG) varies to become deeper inproportion to the power-supply potential V_(DD). This is effective whenthe negative voltage V_(NEG) is used as the well potential of an NMOStransistor, for example. That is, when the NMOS transistor turns off andthe drain voltage attains the power-supply potential V_(DD), leakagecurrent increases when the power-supply potential V_(DD) is high.However, the leakage current is reduced when the well potential (thenegative voltage V_(NEG)) varies to be deeper in proportion to thepower-supply potential V_(DD).

On the other hand, when m>n, the negative voltage V_(NEG) varies tobecome shallower in proportion to the power-supply potential V_(DD). Forexample, when the power-supply potential V_(DD) and the potential of thenegative voltage V_(NEG) are applied between the source and drain of atransistor, the electric field is alleviated even when the power-supplypotential V_(DD) is high, which improves the reliability of thebreakdown voltage of the transistor.

As described in this preferred embodiment, the negative voltage V_(NEG)outputted from the negative voltage generating circuit has dependence onthe power-supply potential V_(DD) when the voltage division ratio of thefirst voltage divider circuit 21 and the voltage division ratio of thesecond voltage divider circuit 31 are set at different values. Thisenables the negative voltage generating circuit to be suitably usedaccording to the purpose of use.

Third Preferred Embodiment

In this preferred embodiment, the negative voltage generating circuit ofthe first preferred embodiment is provided with a current cut (shutdown)function for preventing unnecessary current consumption. That is, whenthe operation of the detector circuit 2 is not needed, a “current cutmode” is selected to cut off the current flowing in the detectorcircuit, and the detector circuit 2 is placed in an idle state to reducethe power consumption.

FIGS. 2A, 2B, and 3 are diagrams used to describe the negative voltagegenerating circuit according to a third preferred embodiment. FIGS. 2Aand 2B are circuit diagrams showing examples of the first voltagedivider circuit 21 of the negative voltage generating circuit, and FIG.3 is a circuit diagram of the comparator circuit 22 of the negativevoltage generating circuit. Except for the first voltage divider circuit21 and the comparator circuit 22, the configuration of the negativevoltage generating circuit of this preferred embodiment is the same asthat shown in FIG. 1. Therefore, only the first voltage divider circuit21 and the comparator circuit 22 will be described below and theremaining components are not described here again.

When the first voltage divider circuit 21 is formed of two NMOStransistors (NMOS transistors N1 and N2) as shown in FIG. 1, the currentcut function can be given to the first voltage divider circuit 21 withthe configuration shown in FIG. 2A, for example. That is, a PMOStransistor P12 is connected in series with the NMOS transistors N1 andN2 to serve as a switching element for cutting off the current flowingto the NMOS transistors N1 and N2.

The gate of the PMOS transistor P12 receives a current cut signalS_(CUT) as a control signal for placing the detector circuit 2 in thecurrent cut mode. When the current cut signal S_(CUT) goes to an Hlevel, the PMOS transistor P12 turns off and cuts off the currentflowing from the power supply V_(DD) to the negative voltage V_(NEG)node (the output terminal of the charge pump circuit 1) through thefirst voltage divider circuit 21 (the NMOS transistors N1 and N2).

However, when the first voltage divider circuit 21 is formed of NMOStransistors, there is a need to give dedicated P well potentials, whichrequires isolation of the P wells. In this case, the formation requiresa relatively large area to surround the bottoms of the P wells with an Nwell.

Accordingly, the first voltage divider circuit 21 may be formed of PMOStransistors. When the first voltage divider circuit 21 is formed of PMOStransistors, there is no need to surround the bottoms of the dedicated Nwells with a P well, which contributes to reduction of the formationarea. The first voltage divider circuit 21 formed of PMOS transistorscan be given the current cut function with the configuration as shown inFIG. 2B, for example.

That is, the first voltage divider circuit 21, for making a voltagedivision between the power supply V_(DD) and the negative voltageV_(NEG), is formed of PMOS transistors P13 and P14, and an NMOStransistor N10 is provided between them as a switching element forcutting off the current flowing thereto. Also, in order to preventfloating of the well potential of the PMOS transistor P14 connected onthe negative voltage V_(NEG) side, a PMOS transistor P15 is provided tofix the detect potential V_(DIV) at the power supply V_(DD).

The gates of the NMOS transistor N10 and the PMOS transistor P15 receivean inversion of the current cut signal S_(CUT) that is inverted by aninverter I4. The inverted signal goes to an L level when the current cutsignal S_(CUT) goes to an H level, and then the NMOS transistor N10turns off to cut off the current flowing from the power supply V_(DD) tothe negative voltage V_(NEG) node (the output terminal of the chargepump circuit 1). At the same time, the PMOS transistor P15 turns on andfixes the well potential of the PMOS transistor P14 at the detectpotential V_(DIV).

Thus, in the negative voltage generating circuit, giving a current cutfunction as shown in FIG. 2A or 2B to the first voltage divider circuit21 reduces the current consumption when the operation of the detectorcircuit 2 is not needed. This is effective when removal of the currentflowing between V_(DD) and negative voltage V_(NEG) is desired, such aswhen the device using the negative voltage generating circuit has a lowpower consumption mode or when an evaluation of the device is made.

FIG. 3 shows a circuit configuration in which the comparator circuit 22has a current cut function. That is, a PMOS transistor P16 is providedin series with the PMOS transistor P3 that supplies a constant currentto the comparator CP, so that the through current flowing from the powerSupply V_(DD) to the negative voltage V_(NEG) through the comparator CPcan be cut off in the current cut mode. Also, an NMOS transistor N11 isprovided in parallel with the NMOS transistor N3 so that the gatepotential of the NMOS transistors N3 and N4, forming a current mirrorcircuit, can be fixed at the ground GND level in the current cut mode.Furthermore, a PMOS transistor P17 is connected between the input end ofthe inverter I1 and the power supply V_(DD) so that the input to theinverter I1 (i.e., the output node of the comparator CP) can be fixed atthe H level in the current cut mode.

The PMOS transistor P16 and the NMOS transistor N11 receive theabove-mentioned current cut signal S_(CUT) and the PMOS transistor P17receives an inversion of the current cut signal S_(CUT) through aninverter I5.

When the current cut signal S_(CUT) goes to the H level, the PMOStransistor P16 turns off and cuts off the through current of thecomparator CP. At the same time, the PMOS transistor P17 turns on andfixes the input of the inverter I1 at the H level to prevent the throughcurrent flowing in the inverter I1 (the detect signal S_(DET) goes tothe L level at this time and the charge pump circuit 1 is inactivated).Also, the NMOS transistor N11 turns on and turns off the NMOStransistors N3 and N4, thus preventing generation of through currentflowing through the PMOS transistor P17 and the NMOS transistor N4. Thatis, the NMOS transistor N11, the PMOS transistors P16, P17, and theinverter I5 form a through current cutting off circuit that cuts off thethrough current flowing in the comparator circuit 22.

When the first voltage divider circuit 21 of FIG. 2A or 2B is combinedwith the comparator circuit 22 of FIG. 3 to form a detector circuit 2,it is possible to cut the consumption current of the entire detectorcircuit 2 in the current cut mode.

Fourth Preferred Embodiment

In the configuration of the negative voltage generating circuit shown inFIG. 1, when the potential of the power Supply V_(DD) is notsufficiently high in a transition state at the time of turning-on of thepower supply, the reference potential V_(REF) stays close to thepotential of the ground GND. At this time, current flows to the PMOStransistors P1 and P2 of the comparator CP but current does not flow tothe NMOS transistors N3 and N4, and the output of the comparator CPexhibits an H level. During this period, the detector circuit 2 outputsthe detect signal S_(DET) at the L level and so the charge pump circuit1 stays inactive. As a result, the start of the operation of the chargepump circuit 1 is delayed, which lengthens the activation time of thenegative voltage generating circuit.

Accordingly, in a fourth preferred embodiment, the detector circuit 2 isconfigured to output the detect signal S_(DET) that activates the chargepump circuit 1 (i.e., the detect signal S_(DET) at the H level) during atransition at the turning-on of the power supply.

FIG. 4 is a diagram illustrating the configuration of the comparatorcircuit 22 of the negative voltage generating circuit of this preferredembodiment. Except for the comparator circuit 22, the circuitconfiguration is the same as that shown in FIG. 1, and therefore onlythe configuration of the comparator circuit 22 will be described belowand the remaining components are not described again.

In this preferred embodiment, as shown in FIG. 4, the polarities (Hlevel/L level) of the output voltage V_(C) of the comparator CP arereversed as compared with those of FIG. 1. An inverter I6 is added sothat the detect signal S_(DET) outputted from the detector circuit 2presents the same logical value as that of FIG. 1.

In the comparator circuit 22 of FIG. 4, when the power-supply voltage isnot sufficiently high, the logical value of the detect signal S_(DET) isdifferent from that of the configuration of FIG. 1. That is, asmentioned above, when the potential of the power supply V_(DD) is notsufficiently high during a transition at a turning-on of the powersupply, current flows to the PMOS transistors P1 and P2 of thecomparator CP but current does not flow to the NMOS transistors N3 andN4. The output voltage V_(C) of the comparator CP of FIG. 4 is then atthe H level. Then, the detector circuit 2 (the inverter I6) outputs thedetect signal S_(DET) at the H level and the charge pump circuit 1 isactivated. That is, the charge pump circuit 1 is activated immediatelyafter the power supply is turned on, which shortens the activation timeof the negative voltage generating circuit.

When the power supply V_(DD) attains a sufficiently high value, thedetector circuit 2 performs ordinary level detecting operation. At thistime, the polarity of the output voltage V_(C) of the comparator CP ofFIG. 4 is opposite to that of FIG. 1, but the detector circuit 2performs the same operation as that of FIG. 1 because of the presence ofthe inverter I6 in the output stage of the detector circuit 2.

According to this preferred embodiment, the charge pump circuit 1 isactivated immediately after the power supply is turned on, whichshortens the activation time of the negative voltage generating circuit.However, with the configuration of the comparator CP of FIG. 4, a largeelectric field is produced in each transistor immediately after thepower supply is turned on, which might deteriorate the reliability ofthe breakdown voltage. Accordingly, the configuration of FIG. 1, wherethe charge pump circuit 1 is kept inactive until the power supply V_(DD)becomes sufficiently high, is preferable when the application requiresensuring the breakdown voltage reliability.

Fifth Preferred Embodiment

In a fifth preferred embodiment, the threshold of the inverter I1receiving the output voltage V_(C) of the comparator CP is set aroundthe middle between the H level potential and the L level potential ofthe voltage V_(C).

FIG. 5 is a diagram illustrating the configuration of the comparatorcircuit 22 of the negative voltage generating circuit of this preferredembodiment. As shown in FIG. 5, the PMOS transistor P5 provided on thepower supply V_(DD) side of the inverter I1 is diode-connected. Theconfiguration is the same as that of FIG. 1 except for the configurationof the comparator circuit 22, and therefore only the configuration ofthe comparator circuit 22 will be described below and the remainingcomponents are not described here again.

The potential of the output voltage V_(C) of the comparator CP varies inthe range from the ground GND to the source potential of the PMOStransistor P2. That is, when the detect potential V_(DIV) is larger thanthe reference potential V_(REF), the potential of the voltage V_(C) isapproximately equal to the ground GND. On the other hand, when thedetect potential V_(DIV) is smaller than the reference potentialV_(REF), the potential of the voltage V_(C) is approximately equal tothe source potential of the PMOS transistor P2.

Accordingly, in the preferred embodiment, the diode-connected PMOStransistor P5 is disposed on the power supply V_(DD) side of theinverter I1, and the channel width size of the PMOS transistor P5 is setso that the threshold of the inverter I1 is around the middle betweenthe source potential of the PMOS transistor P2 and the potential GND ofthe ground GND.

Thus, in this preferred embodiment, the threshold of the inverter I1receiving the output voltage V_(C) from the comparator CP is set aroundthe middle between the H level potential and the L level potential ofthe voltage V_(C), which enlarges the margin of the amplitude of theoutput voltage V_(C) of the comparator CP and enhances the reliabilityof the operation of the detector circuit 2.

Sixth Preferred Embodiment

In the negative voltage generating circuit shown in FIG. 1, the detectpotential V_(DIV) is low when the power supply V_(DD) is low or when thenegative voltage V_(NEG) detected by the detector circuit 2 is deep.When the detect potential V_(DIV) is excessively low, the operation ofthe comparator CP becomes unstable. Accordingly, this preferredembodiment suggests a negative voltage generating circuit that iscapable of performing stable operation even when the detect potentialV_(DIV) is low.

FIG. 6 is a diagram illustrating the configuration of the negativevoltage generating circuit of this preferred embodiment. In FIG. 6, thecomponents corresponding to those of FIG. 1 are shown at the samereference characters (FIG. 6 does not show the charge pump circuit 1).As shown in FIG. 6, a level shift circuit 23 is interposed between thefirst voltage divider circuit 21 and the comparator circuit 22, and alevel shift circuit 33 is interposed between the reference voltagegenerating circuit 3 and the comparator circuit 22. In other respects,the configuration is the same as that of the negative voltage generatingcircuit shown in FIG. 1.

The level shift circuit 23 and the level shift circuit 33 raise thedetect potential V_(DIV) and the reference potential V_(REF) toparticular levels, respectively. That is, in the negative voltagegenerating circuit of FIG. 6, the comparator circuit 22 receives apotential VS_(DIV) obtained by raising the level of the detect potentialV_(DIV) and a potential VS_(REF) obtained by raising the level of thereference potential V_(REF).

Accordingly, even when the power supply V_(DD) is low or when thenegative voltage V_(NEG), detected by the detector circuit 2 is deep,the comparator CP receives relatively large signals and so operatesstably. This enhances the response of the comparator circuit 22 (thedetector circuit 2).

When the level shift circuits 23 and 33 precede the comparator circuit22 as shown in FIG. 6, the comparator circuit 22 may be configured asshown in FIG. 7. That is, the differential pair as the input stage ofthe comparator CP is formed of NMOS transistors N12 and N13, the currentmirror circuit as a load is formed of PMOS transistors P18 and P19, andthe constant-current source for restricting the current flowing to thecomparator CP is formed of an NMOS transistor N14 (a capacitor C2 isprovided to stabilize the reference potential VS_(REF)).

Also, as shown in FIG. 7, the constant-current source for passing aconstant current to the inverter I1 (the PMOS transistor P4 and the NMOStransistor N5) that receives the output voltage V_(C) of the comparatorCP is formed of an NMOS transistor N15. This allows application of acommon voltage V_(CON) to the gates of the NMOS transistor N14 and theNMOS transistor N15.

Seventh Preferred Embodiment

In the present invention, the reference potential V_(REF) outputted fromthe reference voltage generating circuit 3 is susceptible to noisebecause it is generated using small current. Accordingly, in thispreferred embodiment, as shown in FIG. 8, a noise filter circuit 4,composed of a resistor R3 and a capacitor C3, is provided at the node ofthe reference potential V_(REF) (between the reference voltagegenerating circuit 3 and the detector circuit 2). In other respects, theconfiguration of the negative voltage generating circuit is the same asthat shown in FIG. 1.

In this preferred embodiment, the comparator CP in the detector circuit2 receives the reference potential V_(REF) from which noise has beenremoved by the noise filter circuit 4. This prevents the malfunctionthat the detect signal S_(DET) outputted by the detector circuit 2unnecessarily varies due to noise, thus enabling stable operation of thedetector circuit 2. This is especially effective when the detectorcircuit 2 is highly sensitive.

Eighth Preferred Embodiment

In the negative voltage generating circuit of the invention, noise mayoccur in the potential of the negative voltage V_(NEG) at the time ofpower-feeding (activation) by the charge pump circuit 1 or at the timeof current consumption by the semiconductor device. Accordingly, in thispreferred embodiment, as shown in FIG. 9, a noise filter circuit 5,composed of a resistor R4 and a capacitor C4, is provided at the node ofthe negative voltage V_(NEG) (between the charge pump circuit 1 (notshown) and the detector circuit 2). In other respects, the configurationof the negative voltage generating circuit is the same as that of FIG.1.

In this preferred embodiment, the first voltage divider circuit 21 inthe detector circuit 2 receives the negative voltage V_(NEG) from whichnoise has been removed by the noise filter circuit 5. This reduces noisein the detect potential V_(DIV) outputted from the first voltage dividercircuit 21. This prevents the malfunction that the detect signal S_(DET)outputted from the detector circuit 2 unnecessarily varies because ofnoise, thus enabling stable operation of the detector circuit 2. This isespecially effective when the detector circuit 2 is highly sensitive.

This preferred embodiment may be combined with the seventh preferredembodiment. That is, the generative voltage generating circuit of theinvention may include both of the noise filter circuit 4 for removingnoise from the reference potential V_(REF) as shown in FIG. 8 and thenoise filter circuit 5 for removing noise from the negative voltageV_(NEG) as shown in FIG. 9. Removing noise from both of the referencepotential V_(REF) and the negative voltage V_(NEG) inputted to thedetector circuit 2 enables more stable operation of the detector circuit2.

Ninth Preferred Embodiment

In the preferred embodiments described so far, the generation of thedetect potential V_(DIV) in the first voltage divider circuit 21 isachieved by a voltage division between the power supply V_(DD) and thenegative voltage V_(NEG) that is done by the NMOS transistors N1 and N2.A ninth preferred embodiment shows modifications in which the generationof the detect potential V_(DIV) is achieved by using elements other thanMOS transistors.

For example, FIG. 10 is a diagram showing an example in which the firstvoltage divider circuit 21 is formed of capacitors C11 and C12. That is,in this first voltage divider circuit 21, the capacitor C11 and thecapacitor C12 make a voltage division between the power supply V_(DD)and the negative voltage V_(NEG) to generate the detect potentialV_(DIV). In this case, too, the effect of capacitive coupling by thecapacitors C11 and C12 allows the detect potential V_(DIV) to quicklyfollow variation of the negative voltage V_(NEG). This offers the effectdescribed in the first preferred embodiment, i.e., high-speed responsesuperior to those of conventional detector circuits.

Also, FIG. 11 shows an example in which the first voltage dividercircuit 21 is formed of resistors R11 and R12. That is, in this firstvoltage divider circuit 21, the resistor R11 and the resistor R12 make avoltage division between the power supply V_(DD) and the negativevoltage V_(NEG) to generate the detect potential V_(DIV). In this case,the effect of coupling is not obtained, and so high-speed response asdescribed in the first preferred embodiment is not achieved. However,the through current flowing in the first voltage divider circuit 21 isreduced to achieve reduction of power consumption.

Researchers including the inventors of the present invention conductedsimulations using SPICE (Simulation Program With Integrated CircuitEmphasis), and the results showed that the first voltage divider circuit21 using the NMOS transistors N1 and N2 as shown in FIG. 1 exhibitedthrough current variation of about 400 to 500% including those caused byvariation in the manufacturing process (e.g., a variation in the rangeof 1 μA to 5 μA). On the other hand, the first voltage divider circuit21 shown in FIG. 11, using the same polysilicon as the gate electrodematerial as the resistors R11 and R12, reduced the variation to about20% (e.g., a variation in the range of 1 μA to 1.2 μA). That is, thefirst voltage divider circuit 21 of FIG. 11 realizes steady operationwith reduced power consumption, though high-speed response as shown inthe first preferred embodiment is not obtained.

Also, as shown in FIG. 12, the resistors R11 and R12 may be connected inparallel respectively with the capacitors C11 and C12 to form a firstvoltage divider circuit 21. In this case, the capacitors C11 and C12offer the effect of coupling and the resistors R11 and R12 suppressvariation of through current. That is, the first voltage divider circuit21 of FIG. 12 offers both of the superior high-speed response and thestable operation with reduced power consumption. However, it should benoted that, when the area of the formation of the polysilicon resistanceused for the resistors R11 and R12 is large, its parasitic capacitanceis not negligible, and it may hinder full achievement of the effect ofcoupling by the capacitors C11 and C12.

That is to say, as for the elements for forming the first voltagedivider circuit 21, MOS transistors, capacitors, resistors, andcombinations thereof can be suitably selected according to which factorsare important for the application, among high-speed response, themagnitude of consumed current, stability, and area of formation.Particularly, the configuration such as the first voltage dividercircuit 21 shown in FIG. 1, using MOS transistors, will be the mosteffective on the whole, because it is superior in all respects,including high-speed response, the magnitude of consumed current,stability, and area of formation.

In the negative voltage generating circuit shown in FIG. 1, the secondvoltage divider circuit 31, for generating the potential V_(REFO) bymaking a voltage division between the power supply V_(DD) and groundGND, is formed of the resistors R1 and R1. However, the second voltagedivider circuit 31, too, may be formed of MOS transistors, resistors, orcapacitors, like the first voltage divider circuit 21. However, in thenegative voltage generating circuit of FIG. 1, it is not very importantto cause the potential V_(REFO) to quickly vary, and therefore it isdesirable to form the second voltage divider circuit 31 with theresistors R1 and R2 as shown in FIG. 1 to achieve reduction of powerconsumption.

Tenth Preferred Embodiment

As mentioned earlier, the applications of the negative voltagegenerating circuit include semiconductor devices using a PMOS transistoras a DRAM cell transfer gate. This preferred embodiment describes asemiconductor device (DRAM device) including the negative voltagegenerating circuit and DRAM cell according to the invention,particularly a driving circuit for driving a word line to which thecontrol electrode of the transfer gate of a DRAM cell is connected (aword line driver).

FIG. 13 is a circuit diagram of a DRAM cell using a PMOS transistor as atransfer gate, and a conventional common word line driver for drivingthe DRAM cell. As shown in FIG. 13, the word line driver is an invertercircuit formed of a PMOS transistor P21 and an NMOS transistor N21. ThePMOS transistor P21 is connected between a word line WL and a powersupply V_(PP), and the NMOS transistor N21 is connected between the wordline WL and a node of the negative voltage V_(NEG). The gate electrodesof both of the PMOS transistor P21 and the NMOS transistor N21 receive apredetermined control signal CS.

As shown in FIG. 13, the word line WL is connected to the controlelectrode (gate electrode) of a transfer gate TG (PMOS transistor) in aDRAM cell MC. In the DRAM cell MC, one of the source/drain electrodes ofthe transfer gate TG is connected to a bit line BL, while the other isconnected to a capacitor C holding a voltage corresponding to data. Thecapacitor C has the other end connected to a predetermined power supplyV_(CP). With the potential of the power supply V_(CP) being defined as“V_(CP)” and the potential of the common power supply V_(DD) (main powersupply) shown above being defined as “V_(DD)”, those potentials arecommonly set such that 0≦V_(CP)≦V_(DD).

On the basis of the control signal CS, when turning on the transfer gateTG of the DRAM cell MC, the word line driver in FIG. 13 supplies theword line WL with the potential of the negative voltage V_(NEG) (apotential capable of extracting an L (Low) level signal with asufficiently large amplitude from the DRAM cell MC). When turning offthe transfer gate, the word line driver supplies the word line WL withthe potential of the power supply V_(PP) (a potential for preventingleakage of data of the DRAM cell MC). Usually, the power supply V_(PP)is equal to the common power supply V_(DD) (main power supply) shownabove, or is of a higher voltage than that.

As shown in FIG. 13, in the conventional word line driver, the back gateof the PMOS transistor P21 is connected to the power supply V_(PP) andthe back gate of the NMOS transistor N21 is connected to the ground GND.FIG. 14 shows a cross-sectional view of the word line driver and theDRAM cell MC.

As shown in FIG. 14, the word line driver is formed in a P-typesemiconductor substrate (P-type substrate) 40. In the P-type substrate40, a P-type substrate contact region 41 is connected to the ground GND,and so the potential of the P-type substrate 40 is fixed at thepotential of ground GND.

The PMOS transistor P21 is formed in an N well 51 and includes a gateelectrode 52 formed on the N well 51 and a P-type source region 53 and aP-type drain region 54 formed on the sides of the gate electrode 52. Thesource region 53 is connected to the power supply V_(PP) and the drainregion 54 is connected to the word line WL. In the N well 51, an N-typewell contact region 55 is connected to the power supply V_(PP), and sothe N well 51 (i.e., the back gate of the PMOS transistor P21) iselectrically connected to the power supply V_(PP).

The NMOS transistor N21 includes a gate electrode 62 formed on theP-type substrate 40 and an N-type source region 63 and an N-type drainregion 64 formed on the sides of the gate electrode 62. The sourceregion 63 is supplied with the negative voltage V_(NEG) and the drainregion 64 is connected to the word line WL. As mentioned above, theP-type substrate 40 (i.e., the back gate of the NMOS transistor N21) isconnected to the ground GND.

As shown in FIG. 14, the DRAM cell MC is also formed in the P-typesubstrate 40. The transfer gate TG of the DRAM cell MC is formed in an Nwell 81, and includes a control electrode (gate electrode) 82 formed onthe N well 81 and P-type source/drain regions 83 and 84 formed on thesides of the control electrode 82. The capacitor C has a P-type impurityregion 85 connected to the source/drain region 84 as a lower electrode,and is composed of this impurity region 85 and an upper electrode 86formed on the surface of the impurity region 85 via a dielectric film.In the N well 81, an N-type well contact region 87 connected to thepower supply V_(DD) is formed, and so the N well 81 (i.e., the back gateof the transfer gate TG) is electrically connected to the power supplyV_(DD). In the FIG. 14 example, part of the upper electrode 86 entersthe upper part of trench isolation provided with an isolation insulatingfilm 88, thus increasing an effective area of the capacitor C forcapacity increase.

When the negative voltage V_(NEG) is deep in the conventional word linedriver as shown in FIG. 14, current flows from the ground GND to thenode of the negative voltage V_(NEG) through the substrate contactregion 41, the P-type substrate 40, and the source region 63. Then, thepotential of the negative voltage V_(NEG) is fixed at the built-inpotential (Φbi≈−0.5 V) and does not become deeper than that.Accordingly, in this case, it is not necessary to provide the detectorcircuit in the negative voltage generating circuit that generates thenegative voltage V_(NEG). However, the power consumption of the wordline driver is large because of the current flowing from the ground GNDto the node of the negative voltage V_(NEG).

Recently, the widespread use of mobile devices is increasingly demandingreduction of power consumption of DRAM devices used in the mobiledevices. FIG. 15 is a circuit diagram of a word line driver and the DRAMcell according to this preferred embodiment, and FIG. 16 is itscross-sectional view. In FIGS. 15 and 16, the components having the samefunctions as those of FIGS. 13 and 14 are shown at the same referencecharacters.

As shown in FIG. 15, in the word line driver of the preferredembodiment, the back gate of the NMOS transistor N21 is connected to thenegative voltage V_(NEG). In other respects, the circuit configurationis the same as that shown in FIG. 13. The operation is also the same asthat of the word line driver of FIG. 13, and the word line driveroperates on the basis of the control signal CS to supply the potentialof the negative voltage V_(NEG) to the word line WL when turning on thetransfer gate TG of the DRAM cell MC, and supplies the potential of thepower supply V_(PP) to the word line WL when turning off the transfergate.

As shown in FIG. 16, the word line driver of the preferred embodiment isalso formed in a P-type substrate 40. In the P-type substrate 40, aP-type substrate contact region 41 is connected to the ground GND and sothe potential of the P-type substrate 40 is fixed at the potential ofthe ground GND.

The PMOS transistor P21 is constructed as shown in FIG. 14. That is, thePMOS transistor P21 includes a gate electrode 52 on the N well 51 and asource region 53 and a drain region 54 on the sides of the gateelectrode 52. The source region 53 is connected to the power supplyV_(PP) and the drain region 54 is connected to the word line WL. The Nwell 51 (i.e., the back gate of the PMOS transistor P21) is connected tothe power supply V_(PP) through the well contact region 55.

On the other hand, the NMOS transistor N21, unlike that shown in FIG.14, is formed in a P well 61 in an N-type bottom N well 60, and has aso-called “triple well” structure. In this preferred embodiment, thebottom N well 60 and the N well 51 are formed integrally. Therefore, aswell as the potential of the N well 51, the potential of the bottom Nwell 60 is equal to the potential of the power supply V_(PP).

The NMOS transistor N21 includes a gate electrode 62 on the P well 61and a source region 63 and a drain region 64 on the sides of the gateelectrode 62. The source region 63 is supplied with the negative voltageV_(NEG) and the drain region 64 is connected to the word line WL. The Pwell 61 (the back gate of the transistor N21) is supplied with thenegative voltage V_(NEG) through a P-type well contact region 65.

In the structure of FIG. 16, the bottom N well 60 electrically separatesthe P-type substrate 40 at the ground GND potential and the P well 61(negative voltage V_(NEG)) at the negative voltage V_(NEG) potential.Therefore, current does not flow between the ground GND and the node ofthe negative voltage V_(NEG), and the consumed current is smaller thanthat of the word line driver of FIG. 14, which contributes to reductionof power consumption of the DRAM device. However, it should be notedthat the triple well structure may involve a larger area for formation.

In this case, the potential of the negative voltage V_(NEG) can becomedeeper than the built-in potential, so that it is effective to suppressthe variation of the negative voltage V_(NEG) by using the negativevoltage generating circuit having the detector circuit 2 of theinvention. The adoption of the negative voltage generating circuithaving the detector circuit 2 allows arbitrary setting of the level ofthe negative voltage V_(NEG) and quick detection of its variation,thereby allowing stable supply of the negative voltage V_(NEG).Particularly, an application combined with the detector circuit 2 havingthe current cut function shown in the third preferred embodiment furtherreduces the power consumption of the DRAM device.

When the NMOS transistor N21 of the word line driver has a triple wellstructure as shown in FIG. 16, it is effective to form the NMOStransistors N1 and N2 with a triple well structure in the first voltagedivider circuit 21 (FIG. 17) of the negative voltage generating circuitthat supplies the negative voltage V_(NEG) thereto.

FIG. 18 shows a cross-sectional view of the first voltage dividercircuit 21 which adopts the triple well structure. As shown in FIG. 18,the NMOS transistors N1 and N2 are formed respectively in P wells 171and 271 in a bottom N well 70 formed in the P-type substrate 40. Thebottom N well 70 is connected to the power supply V_(DD) through a wellcontact region 71.

The NMOS transistor N1 includes a gate electrode 172 on the P well 171and a source region 173 and a drain region 174 on the sides of the gateelectrode 172, and the NMOS transistor N2 includes a gate electrode 272on the P well 271 and a source region 273 and a drain region 274 on thesides of the gate electrode 272. The P wells 171 and 271 respectivelyhave well contact regions 175 and 275 formed therein as the back gateterminals of the NMOS transistors N1 and N2, respectively.

When the NMOS transistors N1 and N2 of the first voltage divider circuit21 and the NMOS transistor N21 of the word line driver are formed with atriple well structure as shown in FIGS. 16 and 18, they can befabricated in parallel in the same manufacturing process, whichminimizes the complexity of the DRAM device manufacturing process causedby the adoption of the triple well structure.

Also, while this preferred embodiment has shown an example in which thefirst voltage divider circuit 21 is formed of MOS transistors, the firstvoltage divider circuit 21 may be formed of capacitors or resistors asshown in FIGS. 10 to 12.

With respect to the relationship between the absolute value of thepotential of the positive power supply V_(DD) and the absolute value ofthe potential of the negative voltage V_(NEG), it is desirable that theabsolute value of the potential of the positive power supply V_(DD) bethe larger. In that case, the first voltage divider circuit 21 of thedetector circuit 2 shown in FIG. 1 outputs the detect potential V_(DIV)as a positive potential. When the potential of the power supply V_(DD)is from 1.0 to 1.5 V, for example, the potential of the negative voltageV_(NEG) should be set from approximately −0.3 to −0.8.

While the invention has been described in detail, the foregoingdescription is in all aspects illustrative and not restrictive. It isunderstood that numerous other modifications and variations can bedevised without departing from the scope of the invention.

1-11. (canceled)
 12. A semiconductor device comprising a referencepotential generating circuit that generates a reference potential,wherein said reference potential generating circuit includes a firstdivider circuit generating said reference potential by obtaining anintermediate reference potential from a voltage division between a firstvoltage potential and a second voltage potential; and wherein saidreference potential generating circuit further includes an adjustmentcircuit decreasing said reference potential by a predeterminedadjustment value to obtain said reference potential.
 13. A semiconductordevice comprising a detector circuit that detects a level of a firstvoltage, and a reference potential generating circuit that generates areference potential, wherein said detector circuit includes a firstdivider circuit including a plurality of MOS transistors connected inseries between a potential of said first voltage and a potential ofsecond voltage, said plurality of MOS transistors being configured tocause a voltage division between said first voltage potential and saidsecond voltage potential, and said first driver circuit being configuredto output a detect potential generated by the voltage division betweensaid first voltage potential and said second voltage potential; whereinsaid reference potential generating circuit includes a second dividercircuit generating said reference potential by obtaining an intermediatereference potential from a voltage division between said second voltagepotential and a third voltage potential; wherein said referencepotential generating circuit further includes an adjustment circuitdecreasing said reference potential by a predetermined adjustment valueto obtain said reference potential; wherein said detector circuitfurther includes first and second level shift circuits that respectivelyshift said detect potential and said reference potential topredetermined potential levels; wherein said detector circuit furtherincludes a comparator circuit compares said level-shifted detectpotential and said level-shifted reference potential respectivelyoutputted by said first and second level shift circuits; and whereinsaid semiconductor device further comprises a charge pump circuit beingdriven by an output signal from said comparator circuit to generate saidfirst voltage in accordance with said reference potential.
 14. Thesemiconductor device according to claim 2, further comprising: a DRAM(Dynamic Random Access Memory) cell; and a word line driver that drivesa word line of said DRAM cell, said word line driver comprising an NMOStransistor having its drain connected to said word line and its sourcesupplied with said first voltage.